When an embedded processor, such as a PowerPC™, interfaces with a Double Data Rate (DDR) memory in an embedded system, a DDR controller is typically employed to manage the flow of data between the devices. DDR memories transfer data on the rising and falling edges of the clock signal. The DDR controller typically interfaces to the DDR memory device using a Physical (PHY) interface that converts digital signals and commands from the DDR controller logic into waveforms that the DDR memory can interpret.
As the data rates between the DDR memory and embedded processor increase, it becomes increasingly important to determine the delay for each bit through the PHY interface. Thus, a training process is often implemented during the boot time of the embedded processor to properly train the PHY interface.
DDR memories are often divided into sections, referred to as “banks.” This organization results in a minimum or atomic memory area that must be accessed for each read and write operation. Thus, during the training process, the atomic access constraints must be maintained and the delay must be measured for a minimum number of edges. Therefore, a burst mode is typically employed during training to provide a burst of data to analyze all edges at once within an atomic memory area. Generally, the training process reads a data pattern from a portion of the DDR memory and compares the data pattern that was read to the data pattern that was written to the DDR memory portion. If there is an error in the comparison, the training process updates the delay parameters.
The data patterns required for the training process are typically generated using a Direct Memory Access (DMA) engine to ensure a contiguous burst of data that satisfies the atomic memory requirements of the DDR memory. Setting up a DMA engine, however, can consume valuable memory resources and impact the boot performance. In addition, the DDR memory is often used to run code as well. Thus, the DDR memory typically must be functional as soon as possible. Setting up the DMA engine, however, is time consuming and slows down the boot process.
A need therefore exists for improved methods and apparatus for burst transfers of data between DDR memories and embedded processors during training of the PHY interface.